Flat panel display device, method of aging the same, and method of testing lighting of the same

ABSTRACT

A flat panel display device formed in a pentile structure is provided, which includes a pixel portion and a lighting tester. The pixel portion includes a first pixel column, a second pixel column and a third pixel column. In the first pixel column, first pixels for displaying a first color and second pixels for displaying a second color are alternately arranged in a direction the data lines. In the second pixel column, first and second pixels arranged in reverse order of the first pixel column in a direction parallel to the data lines. In the third pixel column, third pixels for displaying a third color are arranged in a direction parallel to the data lines. The lighting tester applies a first voltage to the first pixel column and applies a second voltage to the second pixel column during a first time period. The lighting tester applies the second voltage to the first pixel column and applies the first voltage to the second pixel column during a second time period.

CROSS-REFERENCE TO RELATED APPLICATIONS AND CLAIM OF PRIORITY

This application is a reissue application of U.S. Pat. No. 9,747,831,filed on Jul. 20, 2015 as U.S. patent application Ser. No. 14/804,250and issued on Aug. 29, 2017, which is a continuation application of theprior application Ser. No. 12/385,153 filed in the U.S. Patent &Trademark Office on Mar. 31, 2009 and assigned to the assignee of thepresent invention. Furthermore, this application makes reference to,incorporates the same herein, and claims all benefits accruing under 35U.S.C. § 119 from an application earlier filed in the KoreanIntellectual Property Office on 1 Apr. 2008 and there duly assignedSerial No. 10-2008-0030261.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a flat panel display device formed in apentile structure and having a pixel portion and lighting tester. Thelighting tester applies test voltages or aging voltages to the pixelportion.

Description of the Related Art

Since flat panel display devices are lightweight and thin, they are usedas alternatives to cathode-ray tube display devices. Examples of flatpanel display devices include liquid crystal display (LCD) devices andorganic light emitting diode (OLED) display devices.

The OLED display devices generate excitons by recombination of electronsand holes, which are injected through a cathode and an anode,respectively, in an organic thin film, and emit light having apredetermined wavelength due to energy released from the excitons. TheOLED display devices have high brightness and a wide viewing angle, andcan be embodied in an ultra slim structure because they do not need abacklight.

A flat panel display device includes red, green and blue pixels todisplay full color. When the red, green and blue pixels are arranged instripes, a boundary portion between pixels is visible as though thepixels were surrounded with a black matrix. Thus, image data of the flatpanel display device has to be rendered.

Generally, rendering gives a realistic, three-dimensional appearance toan object by tone variation and shading in consideration of externalinformation such as light sources, perspective and color. That is,rendering is an image-processing technique used to display a two- orthree-dimensional graphic image. To render its image data, the flatpanel display device has to have a plurality of pixels arranged in apentile structure, which includes a first pixel column, a second pixelcolumn, and a third pixel column. In the first pixel column, firstpixels for displaying a first color and second pixels for displaying asecond color are alternately arranged in a direction parallel to aplurality of data lines. In the second pixel column, the first pixelsand the second pixels are arranged in reverse order of the first pixelcolumn in the direction parallel to the plurality of data lines. In thethird pixel column, third pixels for displaying a third color arearranged in the direction parallel to the plurality of data lines.

However, in the flat panel display device having a pentile structuredescribed above, since the first and second pixels are alwaysalternately arranged in one scan line due to the first pixel column inwhich the first and second pixels are alternately arranged in adirection parallel to the plurality of data lines and the second pixelcolumn in which the first and second pixels are arranged in reverseorder of the first pixel column in the direction parallel to theplurality of data lines, a first test voltage for testing lighting ofthe first pixel or a first aging voltage for aging the first pixel, anda second test voltage for testing lighting of the second pixel and asecond aging voltage for aging the second pixel are alternately appliedto one data line during the lighting test or the aging process. Thus, abrightness difference may be generated between pixels during thelighting test, and pixels might be excessively or insufficiently aged.

To solve these problems, it is necessary to either employ additionalequipment for testing or aging each pixel, or modify conventionalequipment for testing and aging a flat panel display device having astriped structure. Thus, additional costs are incurred for the lightingtest and aging process of the flat panel display device having a pentilestructure.

SUMMARY OF THE INVENTION

The present invention provides a flat panel display device which cansufficiently age each pixel of a pixel portion and prevent a brightnessdifference between pixels during a lighting test, without addingequipment or modifying conventional equipment, by changing a structureof a lighting tester for applying lighting test voltages and agingvoltages to the pixel portion through data lines, and lighting test andaging methods for the same.

According to an embodiment of the present invention, a flat paneldisplay device includes a scan driver for applying scan signals to aplurality of scan lines, a data driver for applying data signals to aplurality of data lines, a pixel portion, and a lighting tester forapplying lighting test voltages or aging voltages to the pixel portion.The pixel portion includes a first pixel column including first pixelsfor displaying a first color and second pixels for displaying a secondcolor, a second pixel column including first pixels for displaying thefirst color and second pixels for displaying the second color, and athird pixel column including third pixels for displaying a third color.The first and second pixels of the first column are alternately arrangedin a direction parallel to the data lines, and each of the first andsecond pixels of the first pixel column is coupled to one of the scanlines and one of the data lines. The first and the second pixels of thesecond pixel column are alternately arranged in reverse order of thefirst pixel column in a direction parallel to the data lines, and eachof the first and second pixels of the second pixel column is coupled toone of the scan lines and one of the data lines. The third pixels arearranged in a direction parallel to the data lines, and each of thethird pixels is coupled to one of the scan lines and one of the datalines. The lighting tester applies lighting test voltages or agingvoltages to the first, second and third pixel columns. The lightingtester applies a first voltage to the first pixel column and applies asecond voltage to the second pixel column during a first time period.The lighting tester applies the second voltage to the first pixel columnand applies the first voltage to the second pixel column during a secondtime period.

According to another embodiment of the present invention, a method isprovided for testing lighting of a flat panel display device having thestructure described above. The method includes steps of electricallyconnecting the first pixel column to a first test power source andelectrically connecting the second pixel column to a second test powersource whenever a first control signal is supplied to the lightingtester, electrically connecting the first pixel column to the secondtest power source and electrically connecting the second pixel column tothe first test power source whenever a second control signal is suppliedto the lighting tester, and supplying scan signals to the scan lines.The first and second control signals are synchronized with the scansignals.

According to still another embodiment of the present invention, a methodis provided for aging a flat panel display device having the structuredescribed above. The method includes steps of connecting a first, asecond and a third interconnections to a first, a second and a thirdaging power sources, respectively, electrically connecting the firstpixel column to the first interconnection and electrically connectingthe second pixel column to the second interconnection whenever a firstcontrol signal is supplied to the lighting tester, electricallyconnecting the first pixel column to the second interconnection andelectrically connecting the second pixel column to the firstinterconnection whenever a second control signal is supplied to thelighting tester, electrically connecting the third pixel column to thethird interconnection whenever a third control signal is supplied to thelighting tester, and supplying scan signals to the scan lines. The firstand second control signals are synchronized with the scan signals.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention, and many of the attendantadvantages thereof, will be readily apparent as the same becomes betterunderstood by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings in which likereference symbols indicate the same or similar components, wherein:

FIG. 1 is a schematic view of a flat panel display device according toan exemplary embodiment of the present invention; and

FIG. 2 is a timing diagram of scan and control signals applied to a flatpanel display device according to an exemplary embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the present embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings, wherein like reference numerals refer to the like elementsthroughout. The embodiments are described below in order to explain thepresent invention by referring to the figures.

FIG. 1 is a schematic view of a flat panel display device according toan exemplary embodiment of the present invention.

Referring to FIG. 1, the flat panel display device according to theexemplary embodiment of the present invention includes a data driver 110for applying data signals to a plurality of data lines D1 to Dm, a scandriver 120 for applying scan signals to a plurality of scan lines S1 toSn, a pixel portion 100, and a lighting tester 140 for applying lightingtest voltages or aging voltages to the pixel portion 100. The pixelportion 100 includes a first pixel column 101 in which first pixels PBfor displaying blue color and second pixels PR for displaying red colorare alternately arranged in a direction parallel to the plurality ofdata lines D1 to Dm, a second pixel column 102 in which first pixels PBand second pixels PR are arranged in reverse order of the first pixelcolumn 101 in the direction parallel to the plurality of data lines D1to Dm, and a third pixel column 103 in which third pixels PG fordisplaying green color are arranged in the direction parallel to theplurality of data lines D1 to Dm. The lighting tester 140 for applyinglighting test voltages or aging voltages to the first, second and thirdpixel columns 101, 102 and 103. Each of pixels PR, PB, and PG is coupledto one of the data lines D1 to Dm and to one of scan lines S1 to Sn.

While the exemplary embodiment of the present invention has the firstpixels PB for displaying blue color and the second pixels PR fordisplaying red color alternately arranged in each of the first andsecond pixel columns 101 and 102, in alternative embodiments, the firstpixels PB for displaying blue color and the third pixels PG fordisplaying green color, or the second pixels PR for displaying red colorand the third pixels PG for displaying green color, may be alternatelyarranged in each of the first and second pixel columns 101 and 102.

Moreover, while the pixel portion 100 includes the first pixels PB fordisplaying blue color, the second pixels PR for displaying red color andthe third pixels PG for displaying green color in the exemplaryembodiment of the present invention, the pixel portion 100 may furtherinclude pixels (not illustrated) for displaying one or more colors otherthan red, green and blue.

The data driver 110 receives red, green and blue digital image signalsprocessed by rendering from a timing controller (not illustrated), andgenerates red, green and blue data signals synchronized with the scansignals generated from the scan driver 120. The data driver 110 appliesthe red, green and blue data signals to the pixel portion 100 throughthe plurality of data lines D1 to Dm electrically connected with thepixel portion 100.

The scan driver 120 sequentially applies the scan signals to theplurality of scan lines S1 to Sn electrically connected with the pixelportion 100, and sequentially selects pixels PB, PR and PG from thefirst, second and third pixel columns 101, 102 and 103 of the pixelportion 100, respectively.

The lighting tester 140 includes a first transistor M1 coupled betweenthe first pixel column 101 and a first interconnection Vb through whicha first voltage for a first pixel PB is supplied, a second transistor M2coupled between the first pixel column 101 and a second interconnectionVr through which a second voltage for a second pixel PR is supplied, athird transistor M3 coupled between the second pixel column 102 and afirst interconnection Vb, a fourth transistor M4 coupled between thesecond pixel column 102 and the second interconnection Vr, a fifthtransistor M5 coupled between the third pixel column 103 and a thirdinterconnection Vg through which a third voltage for a third pixel PG issupplied, a first control interconnection C1 through which a firstcontrol signal is applied to turn on the first and fourth transistors M1and M4, a second control interconnection C2 through which a secondcontrol signal is applied to turn on the second and third transistors M2and M3, and a third control interconnection C3 through which a thirdcontrol signal is applied to turn on the fifth transistor M5.

Here, while all of the first to fifth transistors M1 to M5 areillustrated as PMOS transistors in the exemplary embodiment of thepresent invention, the first to fifth transistors M1 to M5 may be NMOStransistors or transistors having different conductivity types from oneanother.

Further, the first, second and third voltages may be lighting testvoltages for testing the lighting of the first, second and third pixelcolumns 101, 102 and 103, respectively, or aging voltages for aging thefirst, second and third pixels PB, PR and PG, respectively. For the testof the lighting, the first, second and third interconnections Vb, Vr andVg are connected to a first, second and third test power sources,respectively. For the aging test, the first, second and thirdinterconnections Vb, Vr and Vg are connected to a first, second andthird aging power sources, respectively.

Since the third voltages have to be sequentially applied to the thirdpixel column 103 in response to the scan signals, the fifth transistorM5 and the third control interconnection C3 may be omitted. However, ifduration of application of the first, second or third voltage to pixelPB, PR or PG of the first, second or third pixel column 101, 102 or 103is shorter than duration of application of a scan signal to each of theplurality of scan lines S1 to Sn (or if a scan signal is applied aheadof the first, second or third voltage applied to the pixel PB, PR orPG), the first, second or third voltage applied to the pixel PB, PR orPG is not sufficiently recorded, which may cause a brightness differencebetween the pixels PB, PR and PG Thus, it is preferable that the fifthtransistor M5 and the third control interconnection C3 are included inthe lighting tester 140.

In addition, the flat panel display device according to the exemplaryembodiment of the present invention may further include an emissioncontroller 130 for applying an emission control signal to the pixelportion 100 to emit light from the first, second and third pixels PB, PRand PG after sufficient lighting test voltages are applied to the first,second and third pixels PB, PR and PG of the pixel columns 101, 102 and103, respectively, during the lighting test for the first, second andthird pixel columns 101, 102 and 103.

FIG. 2 is a timing diagram of signals applied to the flat panel displaydevice according to an exemplary embodiment of the present invention.

According to a driving method during a lighting test or an aging processfor the flat panel display device according to the exemplary embodimentof the present invention, the scan signals are sequentially applied tothe plurality of scan lines S1 to Sn so as to sequentially select pixelsPB, PR and PG from the first, second and third pixel columns 101, 102and 103 of the pixel portion 100, and first and second control signalsare synchronized with the scan signals and applied to the first andsecond control interconnections C1 an C2 of the lighting tester.

Now, voltages applied to the pixel columns 101, 102 and 103 from thelighting tester by the first and second control signals through theplurality of scan lines S1 to Sn to which the scan lines are appliedwill be described with reference to FIG. 2.

First, when a first scan line S1 is selected from the plurality of scanlines S1 to Sn, which can be referred to as a first time period, thefirst transistor M1 coupled between the first pixel column 101 and thefirst interconnection Vb, and the forth transistor M4 coupled betweenthe second pixel column 102 and the second interconnection Vr throughwhich the second voltage for the second pixel PR is supplied, are turnedon in response to a low-level first control signal applied through thefirst control interconnection C1. And, the third transistor M3 coupledbetween the second pixel column 102 and the first interconnection Vb,and the second transistor M2 coupled between the second pixel column 101and the second interconnection Vr, are turned off in response to ahigh-level second control signal applied through the second controlinterconnection C2.

Accordingly, a first voltage is applied to a first pixel PB11 of thefirst pixel column 101 electrically connected with the first scan lineS1, and a second voltage is applied to a second pixel PR13 of the secondpixel column 102 electrically connected with the first scan line S1.

Since a third control signal applied through the third controlinterconnection C3 is in a low level, the fifth transistor M5 coupledbetween the third pixel column 103 and the third interconnection Vg isturned on, and a third voltage is applied to a third pixel PG12 of thethird pixel column 103 electrically connected with the first scan lineS1.

Next, when a second scan line S2 is selected from the plurality of scanlines S1 to Sn, which can be referred to as a second time period, thefirst transistor M1 coupled between the first pixel column 101 and thefirst interconnection Vb, and the forth transistor M4 coupled betweenthe second pixel column 102 and the second interconnection Vr throughwhich a second voltage for the second pixel PR is supplied, are turnedoff in response to a high-level first control signal applied through thefirst control interconnection C1. And, the third transistor M3 coupledbetween the second pixel column 102 and the first interconnection Vb,and the second transistor M2 coupled between the first pixel column 101and the second interconnection Vr, are turned on in response to alow-level second control signal applied through the second controlinterconnection C2.

Accordingly, a first voltage is applied to a second pixel PR21 of thefirst pixel column 101 electrically connected with the second scan lineS2, and a second voltage is applied to a first pixel PB23 of the secondpixel column 102 electrically connected with the second scan line S2.

Since a third control signal applied through the third controlinterconnection C3 is in a low level, the fifth transistor M5 coupledbetween the third pixel column 103 and the third interconnection Vg isturned on, and a third voltage is applied to the third pixel PG22 of thethird pixel column 103 electrically connected with the third scan lineS2.

Here, when the scan signal is applied ahead of the first, second andthird voltages to the respective pixels PB, PR and PG, the first, secondand third voltages applied to the respective pixels PB, PR and PG arenot sufficiently recorded, which may cause a brightness differencebetween the pixels PB, PR and PG. Thus, the first, second and thirdvoltages have to be applied faster than the scan signals by a leadingtime t1 and longer than the scan signal by a lagging time t2 to therespective pixels PB, PR and PG in response to the first, second andthird control signals. That is, the first, second and third voltagesapplied to the respective pixels PB, PR and PG of the first, second andthird pixel columns 101, 102 and 103 have to have larger pulse widthsthan the scan signals applied by the plurality of scan lines S1 to Sn.

Subsequently, when a third scan line S3 is selected from the pluralityof scan lines S1 to Sn, which also can be referred to as the first timeperiod, like when the first scan line S1 is selected as described above,a low-level first control signal is applied through the first controlinterconnection C1, a high-level second control signal is appliedthrough the second control interconnection C2, and a low-level thirdcontrol signal is applied through the third control interconnection C3.Thus, the first transistor M1 coupled between the first pixel column 101and the first interconnection Vb, the fourth transistor M4 coupledbetween the second pixel column 102 and the second interconnection Vrthrough which a second voltage for a second pixel PR is supplied, andthe fifth transistor M5 coupled between the third pixel column 103 andthe third interconnection Vg are turned on. And, the third transistor M3disposed between the second pixel column 102 and the firstinterconnection Vb and the second transistor M2 disposed between thefirst pixel column 101 and the second interconnection Vr are turned off.

Accordingly, a first voltage is applied to the first pixel line 101electrically connected with the first scan line S1, a second voltage isapplied to the second pixel column 102 electrically connected with thefirst scan line S1, and a third voltage is applied to the third pixelcolumn 103.

While the lighting test or aging process is performed on the pixelportion using the lighting tester in the exemplary embodiment of thepresent invention, if the lighting tester includes a lighting test powersource and an aging power source, the lighting test may be performed byconnecting a lighting test voltage source corresponding to each pixel tothe first, second or third interconnection, and then the aging processmay be performed by connecting an aging power source corresponding toeach pixel to the first, second or third interconnection, and viceversa.

As a result, the flat panel display device according to the exemplaryembodiment of the present invention has the first to fourth transistorscontrolled in response to the first and second control signals, whichare disposed between the first and second interconnections and the firstand second pixel columns of the lighting tester. Here, the first andsecond control signals are synchronized with the scan signals andinverted with respect to each other, such that the first or secondinterconnection to which a different voltage is supplied is connectedwith each of the first and second pixel columns having the first andsecond pixels arranged in reverse order to apply a different directcurrent therethrough. Thus, the lighting test or aging process can beperformed for each pixel of each pixel column, and direct lighting testvoltages or direct aging voltages can be applied to correspondingpixels, without adding equipment or modifying conventional equipment.

Consequently, a flat panel display device according to the presentinvention has first pixel column in which first pixels for displaying afirst color and second pixels for displaying a second color arealternately arranged in a direction parallel to a plurality of datalines, and second pixel column in which first and second pixels arearranged in reverse order in a direction parallel to the plurality ofdata lines. The first and second columns are connected with first andsecond interconnections to which different voltages are supplied inresponse to first and second control signals of a lighting tester, bothsignals are synchronized with scan signals such that different directvoltages are applied through the first and second interconnections.Thus, the present invention can test the lighting of each pixel orsufficiently age each pixel of the pixel portion without addingequipment or modifying conventional equipment, and can prevent abrightness difference between pixels during the lighting test.

Although a few embodiments of the present invention have been shown anddescribed, it would be appreciated by those skilled in the art thatchanges may be made in this embodiment without departing from theprinciples and spirit of the invention, the scope of which is defined inthe claims and their equivalents.

What is claimed is:
 1. A flat panel display device, comprising: a scandriver configured to apply scan signals to a plurality of scan lines; adata driver configured to apply data signals to a plurality of datalines; a pixel portion including: a first pixel column including atleast one first pixel configured to display a first color and at leastone second pixel configured to display a second color, the first andsecond pixels of the first column being arranged in a direction parallelto the plurality of data lines; a second pixel column including at leastone first pixel configured to display the first color and at least onesecond pixel configured to display the second color, the first and thesecond pixels of the second pixel column being arranged in a directionparallel to the plurality of data lines, said at least one first pixelof the first pixel column and said at least one second pixel in thesecond pixel column being coupled to the same scan line; and a thirdpixel column including third pixels configured to display a third color,the third pixels being arranged in a direction parallel to the pluralityof data lines, each of the third pixels being coupled to one of the scanlines and one of the data lines; and a lighting tester configured toapply lighting test voltages or aging voltages to the first, second andthird pixel columns, to apply a first voltage to the first pixel columnand a second voltage to the second pixel column during a first timeperiod, and to apply the second voltage to the first pixel column andthe first voltage to the second pixel column during a second timeperiod, both of the first voltage and the second voltage supplied fromtest power sources for lighting the first and second pixel columns orboth of the first voltage and the second voltage supplied from agingpower sources for aging the first and second pixel columns.
 2. Thedevice according to claim 1, wherein a first control signal is suppliedto the lighting tester during the first time period, and a secondcontrol signal is supplied to the lighting tester during the second timeperiod.
 3. The device according to claim 2, wherein the lighting testerincludes: a first transistor electrically connecting the first pixelcolumn to a first interconnection supplying the first voltage wheneverthe first control signal is supplied to the first transistor; a secondtransistor electrically connecting the first pixel column to a secondinterconnection supplying the second voltage whenever the second controlsignal is supplied to the second transistor; a third transistorelectrically connecting the second pixel column to the firstinterconnection whenever the second control signal is supplied to thethird transistor; and, a fourth transistor electrically connecting thesecond pixel column to the second interconnection whenever the firstcontrol signal is supplied to the fourth transistor.
 4. The deviceaccording to claim 3, wherein the first to fourth transistors have thesame conductivity type.
 5. The device according to claim 3, wherein athird control signal is supplied to the lighting tester, a third voltagebeing applied to the third pixel column whenever the third controlsignal is supplied, the lighting tester further including: a fifthtransistor electrically connecting the third pixel column to a thirdinterconnection supplying the third voltage whenever the third controlsignal is supplied to the fifth transistor.
 6. The device according toclaim 5, wherein the first to fifth transistors have the sameconductivity type.
 7. The device according to claim 5, wherein thefirst, second and third voltages are test voltages for testing lightingof the first, second and third pixel columns, or the first, second andthird voltages are aging voltages for aging said at least one firstpixel, said at least one second pixel, and the third pixels.
 8. Thedevice according to claim 1, further comprising: an emission controllerfor controlling emission of said at least one first pixel, said at leastone second pixel, and the third pixels.
 9. The device according to claim1, wherein each of the first color, the second color and the third coloris red, green, or blue, and the first, second, and third colors aredifferent from each other.
 10. A method of testing lighting of a flatpanel display device comprising a plurality of scan lines, a pluralityof data lines, a pixel portion including a first pixel column in whichat least one first pixel configured for displaying a first color and atleast one second pixel configured display for displaying a second colorare arranged in a direction parallel to the plurality of data lines, asecond pixel column in which at least one first pixel and at least onesecond pixel are arranged in a direction parallel to the plurality ofdata lines, and a third pixel column in which third pixels configured todisplay a third color are arranged in a direction parallel to theplurality of data lines, and a lighting tester configured to applylighting test voltages to the first, second and third pixel columnsthrough the plurality of data lines, said at least one first pixel ofthe first pixel column and said at least one second pixel in the secondpixel column being coupled to the same scan line, the method comprising:supplying a first control signal to the lighting tester to cause thelighting tester to electrically connectingconnect the first pixel columnto a first test power source and electrically connectingconnect thesecond pixel column to a second test power sourcewhenever a firstcontrol signal is supplied to the lighting tester, a first voltagesupplied from the first test power source being applied to the firstpixel column, a second voltage supplied from the second test powersource being applied to the second pixel column; supplying a secondcontrol signal to the lighting tester to cause the lighting tester toelectrically connectingconnect the first pixel column to the second testpower source and electrically connectingconnect the second pixel columnto the first test power sourcewhenever a second control signal issupplied to the lighting tester, the second voltage being applied to thefirst pixel column and the first voltage being applied to the secondpixel column, both of the first voltage and the second voltage beingnon-zero lighting test voltages for lighting the first and second pixelcolumns; and supplying scan signals to the scan lines, wherein thesupplying of the first and second control signals being is synchronizedwith the scan signals.
 11. The method according to claim 10, furthercomprising: turning on a first transistor coupled between the firstpixel column and the first test power source and turning on a fourthtransistor coupled between the second pixel column and the second testpower source whenever when the first control signal is supplied; andturning on a second transistor coupled between the first pixel columnand the second test power source, and turning on a third transistorcoupled between the second pixel column and the first test power sourcewhenever when the second control signal is supplied.
 12. The methodaccording to claim 10, further comprising: supplying a third controlsignal to the lighting tester to cause the lighting tester toelectrically connectingconnect the third pixel column to a third testpower sourcewhenever a third control signal is supplied to the lightingtester.
 13. The method according to claim 12, further comprising:turning on a fifth transistor coupled between the third pixel column andthe third test power source whenever when the third control signal issupplied.
 14. The method according to claim 10, further comprising:applying an emission control signal to the pixel portion for controllingemission of said at least one first pixel, said at least one secondpixel, and the third pixels.
 15. A method of aging a flat panel displaydevice comprising a plurality of scan lines, a plurality of data lines,a pixel portion including a first pixel column in which at least onefirst pixel configured display for displaying a first color and at leastone second pixel configured for displaying a second color are arrangedin a direction parallel to the plurality of data lines, a second pixelcolumn in which at least one first pixel and at least one second pixelare arranged in a direction parallel to the plurality of data lines, anda third pixel column in which third pixels configured for displaying athird color are arranged in a direction parallel to the plurality ofdata lines, and a lighting tester configured apply aging voltages to thefirst, second and third pixel columns through the plurality of datalines, said at least one first pixel of the first pixel column and saidat least one second pixel in the second pixel column being coupled tothe same scan line, the method comprising: connecting a first, a secondand a third interconnections to a first, a second and a third agingpower sources, respectively, a first voltage supplied to the firstinterconnection from the first aging power source, a second voltagesupplied to the second interconnection from the second aging powersource; supplying a first control signal to the lighting tester to causethe lighting tester to electrically connectingconnect the first pixelcolumn to the first interconnection and electrically connectingconnectthe second pixel column to the second interconnectionwhenever a firstcontrol signal is supplied to the lighting tester, the first voltagebeing applied to the first pixel column through the firstinterconnection, a second voltage being applied to the second pixelcolumn through the second interconnection; supplying a second controlsignal to the lighting tester to cause the lighting tester toelectrically connectingconnect the first pixel column to the secondinterconnection and electrically connectingconnect the second pixelcolumn to the first interconnectionwhenever a second control signal issupplied to the lighting tester, the second voltage being applied to thefirst pixel column through the second interconnection and the firstvoltage being applied to the second pixel column through the firstinterconnection, both of the first voltage and the second voltage beingnon-zero aging voltages for aging the first and second pixel columns;supplying a third control signal to the lighting tester to cause thelighting tester to electrically connectingconnect the third pixel columnto the third interconnectionwhenever a third control signal is suppliedto the lighting tester; and supplying scan signals to the scan lines,wherein the supplying of the first and second control signals being issynchronized with the scan signals.
 16. The method according to claim15, further comprising: turning on a first transistor coupled betweenthe first pixel column and the first interconnection, and turning on afourth transistor coupled between the second pixel column and the secondinterconnection whenever when the first control signal is supplied;turning on a second transistor coupled between the first pixel columnand the second interconnection, and turning on a third transistorcoupled between the second pixel column and the first interconnectionwhenever when the second control signal is supplied; and turning on afifth transistor coupled between the third pixel column and the thirdinterconnection whenever when the third control signal is supplied. 17.The method according to claim 15, further comprising: applying emissioncontrol signals to the pixel portion to control emission of said atleast one first pixel, said at least one second pixel, and the thirdpixels.
 18. The method according to claim 15, further comprising:connecting the first and second interconnections to a first and a secondtest power sources, respectively; electrically connecting the firstpixel column to the first interconnection and electrically connectingthe second pixel column to the second interconnection whenever when thefirst control signal is supplied; and electrically connecting the firstpixel column to the second interconnection and electrically connectingthe second pixel column to the first interconnection whenever when thesecond control signal is supplied.
 19. The method according to claim 18,further comprising: turning on a first transistor coupled between thefirst pixel column and the first interconnection, and turning on afourth transistor coupled between the second pixel column and the secondinterconnection whenever when the first control signal is supplied; andturning on a second transistor coupled between the first pixel columnand the second interconnection, and turning on a third transistorcoupled between the second pixel column and the first interconnectionwhenever when the second control signal is supplied.
 20. The methodaccording to claim 19, further comprising: turning on a fifth transistorcoupled between the third pixel column and the third interconnectionwhenever the third control signal is supplied.
 21. The method accordingto claim 18, further comprising: connecting the third interconnection toa third test power source; and electrically connecting the third pixelcolumn to the third interconnection whenever when the third controlsignal us is supplied.
 22. The method according to claim 19, furthercomprising: turning on a fifth transistor coupled between the thirdpixel column and the third interconnection when the third control signalis supplied.
 23. A display device, comprising: a scan driver configuredto apply scan signals to a plurality of scan lines; a data driverconfigured to apply data signals to a plurality of data lines; aplurality of first pixels disposed in a first column, configured todisplay a first color, and electrically connected to a first data lineof the data lines; a plurality of second pixels disposed in the firstcolumn, configured to display a second color, and electrically connectedto the first data line of the data lines; a plurality of third pixelsdisposed in a second column, configured to display a third color, andelectrically connected to a second data line of the data lines; and alighting tester comprising: a first transistor including an endelectrically connected to the first data line; a second transistorincluding an end electrically connected to the first data line; a thirdtransistor including an end electrically connected to the second dataline; a first interconnection connected to another end of the firsttransistor; a second interconnection connected to another end of thesecond transistor; a third interconnection connected to another end ofthe third transistor; a first control interconnection connected to agate of the first transistor; a second control interconnection connectedto a gate of the second transistor; and a third control interconnectionconnected to a gate of the third transistor, wherein the firstinterconnection is configured to supply a first voltage, the secondinterconnection is configured to supply a second voltage, and the thirdinterconnection is configured to supply a third voltage, wherein thefirst control interconnection is configured to supply a first controlsignal, the second control interconnection is configured to supply asecond control signal, and the third control interconnection isconfigured to supply a third control signal, wherein the lighting testeris disposed outside of an area where the first, the second, and thethird pixels are disposed, wherein both of the first voltage and thesecond voltage are supplied to the first column through the first dataline, and wherein each of the first voltage, the second voltage, and thethird voltage is supplied from test power sources for lighting thefirst, second, and third pixel columns, or each of the first voltage,the second voltage, and the third voltage is supplied from aging powersources for aging the first and second columns.
 24. The display deviceaccording to claim 23, wherein one of the first pixels and one of thesecond pixels is alternately connected to the first data line.
 25. Thedisplay device according to claim 24, further comprising: a third dataline; a plurality of fourth pixels disposed in a third column,configured to display the first color, and electrically connected to thethird data line of the data lines; and a plurality of fifth pixelsdisposed in a third column, configured to display the second color, andelectrically connected to the third data line.
 26. The display deviceaccording to claim 25, wherein one of the fourth pixels and one of thefifth pixels are alternately connected to the third data line.
 27. Thedisplay device according to claim 26, wherein the second data line isarranged in between the first data line and the third data line.
 28. Thedisplay device according to claim 27, further comprising: a fourthtransistor including an end electrically connected to the third dataline; a fifth transistor including an end electrically connected to thethird data line; a fourth interconnection connected to another end ofthe fourth transistor; and a fifth interconnection connected to anotherend of the fifth transistor, wherein the first control interconnectionis connected to a gate of the fifth transistor, and wherein the secondcontrol interconnection is connected to a gate of the fourth transistor.29. The display device according to claim 23, further comprising: anemission controller configured to control emission of one of the firstpixels, one of the second pixels, and one of the third pixels.
 30. Thedisplay device according to claim 29, wherein one of the first pixelsand one of the second pixels are alternately connected to the first dataline.
 31. The display device according to claim 30, further comprising:a third data line; a plurality of fourth pixels disposed in a thirdcolumn, configured to display the first color, and electricallyconnected to the third data line of the data lines; and a plurality offifth pixels disposed in a third column, configured to display thesecond color, and electrically connected to the third data line.
 32. Thedisplay device according to claim 31, wherein one of the fourth pixelsand one of the fifth pixels are alternately connected to the third dataline.
 33. The display device according to claim 32, wherein the seconddata line is arranged in between the first data line and the third dataline.
 34. The display device according to claim 33, further comprising:a fourth transistor including an end electrically connected to the thirddata line; a fifth transistor including an end electrically connected tothe third data line; a fourth interconnection connected to another endof the fourth transistor; and a fifth interconnection connected toanother end of the fifth transistor, wherein the first controlinterconnection is connected to a gate of the fifth transistor, andwherein the second control interconnection is connected to a gate of thefourth transistor.